The present invention relates to network devices and particularly to network switches for packet-based communication systems such as Ethernet networks and also to an improved method of operating such a network device or switch. The term xe2x80x98switchxe2x80x99 is intended to refer broadly to a device which receives addressed data packets at any of a multiplicity of physical xe2x80x98portsxe2x80x99 and which can internally switch those packets so that received packets are forwarded from one or more ports in response to the address data in the packet or modified forms of such address data.
Broadly, switches of the kind to which the invention relates have a multiplicity of physical ports at which addressed data packets can be received. The data traffic, and therefore the occupancy of bandwidth, at any particular port may vary widely. Typically, a switch includes means for temporarily storing packets received by the input ports and means, hereinafter called for convenience xe2x80x98output bufferxe2x80x99, for the temporary storage of data packets before they are forwarded from a port. Such means might be constituted by individual FIFO stores, by respective allocated memory space within a dynamic random access memory or by other forms of memory. Normally the switch includes a forwarding database which is built up typically by the reading of source addresses in incoming packets. The forwarding database permits, from an examination of a received packet and from recourse to associated data, the determination of the or each port from which a received packet should be dispatched. Packets having destination addresses which do not appear in the database need to be xe2x80x98broadcastxe2x80x99 either throughout the whole of the network or part of it in order to achieve resolution of the address. Generally, switches which rely on media access control, otherwise called xe2x80x98layer 2xe2x80x99, addresses are termed xe2x80x98bridgesxe2x80x99 whereas switches which rely on logical link control, otherwise known as xe2x80x98layer 3xe2x80x99, addresses are normally termed xe2x80x98routersxe2x80x99. In almost all switches of this general kind there is a conflict of bandwidths required for different types of packet. In any practical system the buffer space available for the transmitting ports of a switch is limited and accordingly switches in practice are inherently liable to congestion.
Various techniques are currently used to bridge and/or route data packets of different types. These techniques generally rely on the individual packets"" protocols or priorities to influence the speed of transmission through the switch and/or to determine whether packets will be discarded if the device becomes congested. Generally, packets of higher priority experience the lower rate of discard.
In British patent application number 9807264.8 filed Apr. 3, 1998 (published as GB-2336076-A) and corresponding U.S. patent application Ser. No. 09/093,287 (Moran et al) there is described a mechanism for limiting the aggregate traffic through a port of a network device. The mechanism essentially comprises a counter which increments in accordance with the sizes of packets through the port and decrements at a rate which determines the maximum allowed data rate through the port. The decrementing rate may be remotely controlled by a network administrator. The traffic through the port is limited, if the content of the counter exceeds a threshold, by initiating xe2x80x98flow controlxe2x80x99, that is to say the sending of control packets to the other end of the link to which the port is connected. These control packets are, in accordance with a known transmission standard, in a form which instructs the device at the far end of the link to cease sending packets for some period of time specified in the control packet. The proposal does not enable either any distinction to be made between packets of different type or the setting of a maximum bandwidth for traffic of a particular type.
The present invention particularly relates to an improved and more versatile technique for allocating a maximum bandwidth which may be occupied by packets of a particular type in an output link.
In a preferred form of the invention, bandwidth allocation for at least one defined packet type is achieved using a single buffer memory space. Different packet types are selected by for example snooping the protocol fields of packets and/or priority fields in the packets and categorising the packets according to the selection. For at least one and preferably each selected packet type there is a means which determines whether there are enough credits to store a new packet in the output buffer. Each time a new packet is accepted, a respective aggregate count is decremented by the size of the packet. Meanwhile, the aggregate count is constantly incremented at a selectable or controlled rate. In one embodiment of the invention, a counter may be incremented in response to a proportion of pulses corresponding to or defining the speed of a port. For example, if the desired maximum bandwidth to be occupied by packets of a selected type in an output link is to be 30% of the available bandwidth on that link, a counter for packets of that particular type may be incremented in response to three out of each ten successive clock pulses. Alternatively pulses corresponding to slot pulses for an internal slotted bus may be used if it is desired that the counting be independent of the speed of the port.
In an idle state, the counter may be incremented up to the allocation of the output buffer and may thereby store enough xe2x80x98creditsxe2x80x99 for bursty traffic.